’ Introduction RELIABILITY - AWARE MICROARCHITECTURE

It is becoming increasingly difficult to achieve expected levels of reliability and data correctness as the industry approaches the era of extreme CMOS scaling. Aging-related device degradation is becoming a real threat to lifetime reliability. Many processors already include solutions for soft errors in memory structures. More recently, soft errors in logic paths have become an increasing concern. Process variability effects are challenging conventional design as the law of large numbers is no longer useful for describing device behavior, and design based on worstcase paths becomes impractical. Impending problems with burn-in and timing effects from temperature are additional threats to reliable operation. In the past, architects have often left reliability concerns to lower levels of the system stack. As the severity of these problems increases, however, low-level solutions will likely not suffice, and straightforward systemlevel solutions such as blind redundancy will likely be too expensive for most market segments. Architects will therefore need to make reliability a first-class design constraint and develop new cost-effective approaches to reliability-aware design. Compared to device and circuit-level solutions, architecture-level solutions can more easily exploit application-specific behavior. For example, for common applications, a large fraction of raw soft errors are masked at the architecture level, potentially allowing for lower-cost solutions at this level. As another example, architecture-level solutions offer the opportunity for application-driven dynamic lifetime reliability management, allowing an optimal distribution of failure rates in time and space. Sarita V. Adve